DESIGN AND IMPLEMENTATION OF FPGA BASED G CODE COMPATIBLE CNC

DESIGN AND IMPLEMENTATION OF FPGA BASED G CODE COMPATIBLE CNC

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For the first time a G code based, CNC Lathe controller is designed and implemented in a FPGA, with its heart being a 4 stage Multi InstructionMulti Data (MIMD) Complex Instruction Set computers (CISC) G code processor. The conventional machining done in the past like lathe and milling operations were done manually. Accuracy and consistency between two produced parts vary tremendously due to human errors and limitations. With the advent of processor and controllers, came the Computerized Numerically Controlled (CNC) machines, having the advantage of using universally accepted G code machining language to machine the parts. It became really easy to produce the parts with same accuracies and consistency on different machines with the same G code being used. G codes are CNC machine assembly language having various Interpolation Instructions G codes, Tool Instruction T codes, Feed-rate Instruction F codes, Principal Axis Speed Instruction S codes and various Controlling and Input - Output Instructions M codes. G code based CNC systems available till date, are implemented using controllers and processors using software interpolation. Software implementation of complex interpolation algorithms by serial pipelined processors is time consuming, difficult and impractical for real time applications. Thus the efficient, real time complex computation approach is only feasible with hardware logic circuits like FPGA or ASIC having parallel and low power processing architectures. In the presented work, for the first time a G code based, CNC Lathe controller is designed and implemented in a FPGA. It is implemented and validated on Xilinx Artix 7, 7a100tcsg324-1 FPGA based kit, with its heart being a 4 stage Multi InstructionMulti Data (MIMD) Complex Instruction Set computers (CISC) G code processor. The Rapid Positioning Controller, Linear Interpolation Controller and Circular Interpolation Controller are also designed as a co-processor for the G Code

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